Field of the Invention
The invention relates to an integrated semiconductor configuration having a semiconductor substrate of a first conductivity type being connected to a first supply potential, having a first region in which switching stages are disposed and having at least a second region in which at least one connecting line is disposed for connecting signal terminals of the switching stages, a number of doping zones being provided in the second region and having a second conductivity type complementary to the first conductivity type, the doping zones being connected to a second supply potential, and at least a portion of a total surface area of the doping zones being located under the connecting line.
One such integrated semiconductor configuration is known from U.S. Pat. No. 5,136,357.
In integrated semiconductor configurations, a parasitic capacitor is active between the signal line that connects the output of one switching stage to the input of a further switching stage and the supply potential with which the semiconductor substrate is contacted. Upon switchover of the switching stage, the level of the signal line changes from H to L or vice versa. Consequently, the charge of the parasitic capacitor is also reversed. At a signal edge at which the capacitor is discharged, the discharge current flows as a short-circuit current across the components connected between the capacitor electrodes. At the signal edge at which the capacitor is charged, the charge current is furnished by the supply voltage source of the semiconductor configuration.
If a number of switching stages switch over synchronously, then such a high current pulse can arise on the connecting lines between the supply voltage source and the integrated switching stages on the semiconductor configuration that the parasitic inductors of the connecting lines become operative, and pulse-like voltages drop there. The supply voltage applied to the switching stages then drops during the switchover process. That lessens the security of the signals against interference. The parasitic inductors counteract the current pulse, so that a lesser current is available for reversing the charge of the parasitic capacitors of the signal lines connected on the output side to the switching stages. That increases the signal transit time.
In an integrated semiconductor configuration known from U.S. Pat. No. 5,136,357, the influence of the parasitic capacitors that are operative along the signal line is reduced by providing a number of doping zones in the second region that have a second conductivity type which is complementary to the first conductivity type, in which the doping zones are connected to a second supply potential, and in which at least some of the total surface area of the doping zones is located under the connecting line.
However, in the known semiconductor configuration, the first regions are distributed arbitrarily over the substrate, so that for any existing connecting line, a suitably located doping zone must be created, which then necessarily means that the doping zones are also distributed arbitrarily over the substrate. That involves considerable effort and expense in converting the particular circuit provided in the semiconductor configuration into masks for the production process.